1. Field of the Invention
The present invention is directed to flash memory array access method and device, and in particular to an improved flash memory array access method and device capable of reducing a search time between a logical address from a host and a physical address and improving an access time of the memory.
2. Description of the Background Art
Modern computer systems or digital systems utilize a memory such as a hard disk. However, the hard disk is heavy in weight, has large capacity and consumes a significant amount of electricity. Recently, a flash electrically erasable programmable read only memory EEPROM has been popularly used as a memory device capable of overcoming the aforementioned disadvantages. In addition, the flash EEPROM is reprogrammable, and thus it can be used for updating software connected with system operation.
However, unlike an EEPROM, the flash EEPROM is only reprogrammable after its entire memory array is erased. That is, the flash EEPROM cannot be reprogrammed before being erased.
The flash EEPROM is erased by simultaneously applying a high voltage to source terminals of all transistors (cells) used in the memory. However, the time to perform this erasure is relatively long. Therefore, in order to efficiently perform an erase operation, the memory array is divided into a plurality of blocks, and then memory elements in a corresponding block can be separately erased. The respective blocks include at least two or more sectors that are also managed by the host. Each sector has a user region and an overhead region. The overhead region serves to store the erase frequency information such as an erase cycle frequency.
For example, U.S. Pat. No. 5,341,339 entitled xe2x80x9cMETHOD FOR WEAR LEVELING IN A FLASH EEPROM MEMORYxe2x80x9d to Wells, hereby incorporated by reference in its entirety, is related to a flash EEPROM. In this patent, in order to solve a problem that some memory elements are more frequently erased than the other memory elements and finally become unusable, there is provided a method of equally erasing memory cells by using the erase frequency information. Furthermore, there is described a method of using a lookup table to know the relationship between the physical address and the logical address managed by the host in writing data to a memory array divided into blocks. FIG. 1 is a schematic block diagram illustrating how a memory array constituted by using a conventional flash EEPROM is utilized.
In order to access the memory array 1, the memory array 1 of the conventional flash EEPROM receives a logic address from the host (not illustrated) and generates the physical address corresponding to the logical address. Here, a control unit 2 accessing the memory array 1 and providing a data to the host is used. The control unit 2 includes: an address conversion block 3, which stores a lookup table determining the relationship between the logical address and the physical address, a first database listing the amount of free space in each block of the memory array 1 and the total amount of free space, and a second database listing the amount of invalid data in each block and the total amount of invalid data; and a memory control unit 4 providing the received physical address to the memory array 1 and further providing or receiving a data or table information to or from the memory array 1.
In the case that there is a data that will updated, the previously-stored block containing that data is not erased, but the data is sequentially stored in a vacant space in the memory array. The previously-stored data is managed as invalid data, the block containing the data is erased afterward, and thus it is necessary to determine the relationship between the logical address managed by the host and the physical address. The address conversion block 3 is utilized for such a process. Accordingly, the memory control unit 4 serves to control read and output, write or erase operations of the information connected with the sectors in the blocks where the physical address is designated. The plurality of blocks (not illustrated) composing the memory array 1 respectively include a separate region having the table information as in the lookup table stored by the address conversion block 3.
The data read and output operation from the memory array 1 will now be described.
The read and output operation is started when the control unit 2 illustrated in FIG. 1 receives the logical address from the host. Here, in order to carry out a series of processes, a microprocessor (not illustrated) of the control unit 2 refers to the lookup table of the address conversion block 3 and obtains the physical address pursuant to the relationship between the logical address and the physical address. If there is a corresponding physical address, a valid data included in the physical sector is outputted to the host by using the physical address.
The write operation will now be explained. The host provides the logical address to the control unit 2 illustrated in FIG. 1, as in the read and output operation. At this time, the corresponding physical address is firstly obtained by referring to the lookup table. The lookup table information that corresponds to the provided logical address is invalidated, the first and second databases are updated, and whether a sector which is not presently used in the lookup table exists is determined (i.e., a physical address with no associated logical address). In case there is a vacant usable sector, the data transmitted from the host is written in a physical position of the corresponding sector.
The data can be read afterward by updating the lookup table for the sector. In the case that a usable sector does not exist, the lookup table information that corresponds to the provided logical address is still invalidated and the first and second databases updated. However, the remainder of the write operation is carried out after the erase operation.
The erase operation will now be explained. The block that does not have valid data or has the least amount of valid data is selected using the second database. Selection of the block for erasure can also depend on the number of erasures each block has undergone such as described in U.S. Pat. No. 5,341,339.
In regard to the block that does not include the valid data, a portion of the lookup table connected with the block and the table information in the memory array 1 are amended, the erase operation is performed on the block that will be erased, and then the remainder of the write operation is carried out. The erase operation is performed by applying, for example, a voltage of 12 V to a source of a floating-gate field-effect transistor composing the memory cell.
In the case the block that will be erased includes valid data, the valid data is transmitted to a portion of the memory array 1 set aside for dealing with part of the erase operation. Then, the corresponding lookup table and table information are amended and the erase operation is carried out. Subsequently, the remainder of the write operation takes place.
As described so far, the lookup table is very important in using the memory in the conventional art. However, the conventional method has a disadvantage in that it takes relatively long time to carry out the read and output operation or to search the lookup table for obtaining the physical address of the sector that the host will access.
Also, when the write operation is performed, the lookup table for invalidating a previously-written sector must be searched, which requires a considerable amount of time.
The method and device for accessing a flash memory array accesses a flash memory array divided into a plurality of blocks. Each block includes logical address to physical address conversion information for that block. After determining to which block a received logical address corresponds, the method and device obtain the conversion information for that block, store the obtained conversion information, and then perform a memory access operation based on the received logical address and the stored conversion information. In this manner, only conversion information for a block is searched to perform a memory access operation, instead of conversion information for the entire flash memory array as in the conventional art.
Accordingly, the present invention provides an improved high-speed flash EEPROM access method and device capable of processing data at high-speed.